In present day circuits, memories play a vital role. Memories are verified thoroughly in their development phase before they enter into production phase. Memories are designed with less area and less marginalities to increase the speed and performance. So in the development phase, memories are much more prone to failures as compared to production phase. Hence proper methods for testing and debugging are very essential in the development phase.
In the development phase, memories are tested in all the conditions that they might face when used as a part of bigger system. Verification tests are designed such that they catch not only static defects but also dynamic defects. Static faults include defects such as stuck at, open circuit and short circuit faults. Dynamic faults include faults such as timing sensitive defects that may be due to weak pull-up or weak pull-down transistors. The number of patterns applied to validate the memory depends upon the size of memory and becomes very large for high capacity memories.
A specialized device tester is normally required to perform these tests on the circuit. All the patterns are loaded in the tester memory and tester runs them one by one. These patterns include read/write verification cycles designed in such a way that they sensitize the defects so that they can be caught. Relatively low cost and low speed device testers are usually used for detecting static faults. But these are not sufficient to detect dynamic faults in high-speed memories. For such high speed memories very expensive and high-speed testers are required. These expensive high-speed testers increase the overall cost of the devices.
Also, with the introduction of deep submicron and nanometer technologies, these needs have increased dramatically. The new technologies impact coupling and noise margins adversely and make integrating on-line test in modern integrated circuits mandatory.
Memories can be tested through an external device tester. Memories are accessed through I/O pads of the chip. The external tester applies extensive patterns on the memory. One such programmable memory test interface is disclosed in U.S. Pat. No. 5,968,192. The test interface includes logic circuitry configured to be integrated to a memory device. The memory device has a plurality of receiving connections that are configured to be coupled to a plurality of internal connections that couple to the logic circuitry. The interface further includes a plurality of programmable input pins and output pins leading to and from the logic circuitry, and the programmable input pins and output pins are configured to receive control signals from a test controller for operating the memory device in either a test mode or a mission mode. The programmable input pins and output pins are selectively interconnected to transform the logic circuitry into at least one type of memory testing methodology interface.
Built-In Self Test (BITS) circuits are another popular approach used for on-chip at speed testing of memories. Built-In Self Test (BITS) circuits have patterns/algorithms hard cored inside them. These patterns are applied on the memory at speed. Comparator inside the BITS monitors the response of the memory and generates pass/fail signal accordingly. The limitations of this approach are—Patterns other than hard corded cannot be applied.
Area of the BITS increases with increase in number of patterns.
BITS doesn't give much information about the cause of the failure.
They are inefficient for debugging process.
U.S. Pat. No. 6,230,290 discloses one such method of self-programmable Built In Self Test (BITS) for a memory (e.g., Dynamic Random Access Memory (DRAM)). The DRAM, which may be a DRAM chip, includes a DRAM core, a Microcode or Initial Command ROM, a BITS Engine, a Command Register and a Self-Program Circuit. During self test, the BITS engine may test the DRAM normally until an error is encountered. When an error is encountered, the Self-Program Circuit restarts the self test procedure at less stringent conditions. Optionally, when the DRAM tests error-free, the Self-Program Circuit may restart testing at more stringent conditions to determine DRAM functionality limits.
U.S. Pat. No. 6,321,320 elaborates a highly flexible and complex BITS engine provides at-speed access, testing, characterization, and monitoring of on-chip memory arrays, independent of other chip circuitry such as a CPU core. Each BITS engine has a main control block, at least one address generation block having an address local control block and one or more address-data generation blocks, and at least one data generation block having a data local control block and one or more data generation blocks. Each of the local address and data control blocks are programmed independently to define operations that will be performed by the individual address and data generation blocks, respectively. The main control block in turn controls operation of the local address and data control blocks to effect desired testing, accessing, and monitoring of the on-chip memory arrays.
U.S. Pat. No. 6,044,481 presents a programmable memory test interface for testing a memory device. The interface includes a plurality of programmable input pins and output pins. The interface also includes a logic interfacing means for connecting external signals to the plurality of programmable input pins and output pins. The external signals are processed by the logic interfacing means and then communicated to a plurality of memory connection pins that couple up to the memory device. The logic component means is capable of being configured in accordance with one or more memory testing methodologies including a serial built-in-self-test (BITS), a parallel built-in-self-test (BITS), a parallel test, a serial test, and a scan test. The configuring is performed by selectively interconnecting selected ones of the plurality of input pins and output pins to the external signals that drive the logic interface means in a test mode that operates in one or more memory testing methodologies or a mission mode.
The limitations of BITS circuits are—
Very expensive tester is required for testing.
Memories cannot be tested at speed because of low speed of I/O pads.
The tester memory, which stores the test pattern, limits the number of patterns.
Programmable BITS overcome the limitation of fixed patterns but their limitations are—
Difficulty in programming and usage.
Non-standard codes for operations. Non-standard way of programming the algorithms.
Generation of bits sequence for algorithm is manual.
Different types of memories have different types of controllers and hardware sharing is not possible.
Direct memory test and BITS don't help much for debugging memories. They can only help in finding if a particular pattern has run successfully or not. With the increase in overall manufacturing cost and difficulty in detecting at-speed tests, the demand for cost-effective and on-line testing has increased. In addition, there is a higher demand for on-chip characterization circuits, which accurately characterize the circuits thereby, helping greatly in debugging faulty IC's.